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-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LEDseq is
    Port ( CLK : in  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (7 downto 0));
end LEDseq;

architecture LEDseq of LEDseq is
  component MyBRAM is Generic (N: integer:=1024; W:integer:=16 );
    Port ( CLK : in  STD_LOGIC;
           Din : in  STD_LOGIC_VECTOR (7 downto 0);
           Adr : in  integer range 0 to 1023;
           Dout : out  STD_LOGIC_VECTOR (7 downto 0);
           WE : in  STD_LOGIC;
           EN : in  STD_LOGIC);
  end component;
  signal cntr_for_array: integer range 0 to 10;
  signal cntr: integer range 0 to 25000000;
  signal EN: STD_LOGIC;

begin
  MyRinst: MyBRAM Generic map (N=>1024,W=>8)
  port map (
    CLK => CLK,
    Din => "00000000",
    Adr => cntr_for_array,
    Dout => LED,
    WE => '0',
    EN => EN
  );
  process(CLK) is begin
    if(rising_edge(CLK)) then
      if(cntr=25000000) then
        EN <='1'; cntr <= 0; 
        if(cntr_for_array=10) then 
          cntr_for_array <=0;
        else 
          cntr_for_array <= cntr_for_array+1; 
        end if;
      else
        EN <='0'; cntr <= cntr+1;
      end if;  
    end if;
  end process;

end LEDseq;