----------------------------------------------------------------------------------
-- Block Ram Inference
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
library UNISIM;
use UNISIM.VComponents.all;

entity MyBRAM is Generic (N: integer:=1024; W:integer:=16 );
    Port ( CLK : in  STD_LOGIC;
           Din : in  STD_LOGIC_VECTOR (W-1 downto 0);
           Adr : in  integer range 0 to N-1;
           Dout : out  STD_LOGIC_VECTOR (W-1 downto 0);
           WE : in  STD_LOGIC;
           EN : in  STD_LOGIC);
end MyBRAM;

architecture MyBRAM of MyBRAM is
  type MyRAMtype is array (0 to N-1) of STD_LOGIC_VECTOR(W-1 downto 0);
  
  function initR(RamSize:integer) return MyRAMtype is
    variable rv: MyRAMtype;
  begin
    for i in 0 to RamSize-1 loop
      rv(i) := std_logic_vector(to_signed(integer( round(real(real(2**(W-1))*cos(real(MATH_PI)*real(i)/real(2*N)))) ),W));
    end loop;
    return rv;
  end initR;
  
  --signal MyR : MyRAMtype := (x"01",x"AA",x"55",x"0F",x"F0",x"CC",x"33",x"10",x"40",x"10",x"40",others=>x"00");
  signal MyR : MyRAMtype := initR(N);  
begin
  MR:process(CLK) is begin
    if(rising_edge(CLK)) then
      if(EN='1') then
        Dout <= MyR(Adr);
        if(WE='1') then
          MyR(Adr) <= Din;
        end if;
      end if;
    end if;
  end process;

end MyBRAM;