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-- Key Debouncer
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity keydebouncer is
    Port ( CLK : in  STD_LOGIC;
           Kin : in  STD_LOGIC;
           Kout : out  STD_LOGIC);
end keydebouncer;

architecture Behavioral of keydebouncer is
  constant DELAY : integer := 1000000;
  signal cntr : integer range 0 to DELAY;
  signal FF : STD_LOGIC_VECTOR(2 downto 0);
begin
  process(CLK,cntr,FF,Kin) is begin
    if(rising_edge(CLK)) then
      if(cntr=DELAY) then
        cntr <= 0;
        FF <= FF(1 downto 0) & Kin;
        if(FF="111") then Kout <= '1';
        elsif(FF="000") then Kout <= '0'; end if;
      else
        cntr <= cntr+1;
      end if;
    end if;
  end process;

end Behavioral;

----------------------------------------------------------------------------------
-- Key Sequence Reader
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity quiz1 is
    Port ( CLK : in  STD_LOGIC;
           btn0 : in  STD_LOGIC;
           btn1 : in  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (7 downto 0));
end quiz1;

architecture Behavioral of quiz1 is
  component keydebouncer is Port ( CLK,Kin : in  STD_LOGIC; Kout : out  STD_LOGIC); end component;
  signal pD0, D0, pD1, D1 : STD_LOGIC;
  signal SEQ : STD_LOGIC_VECTOR(7 downto 0);
begin
  db0: keydebouncer port map (CLK,btn0,D0); 
  db1: keydebouncer port map (CLK,btn1,D1); 

  process(CLK,SEQ,D0,D1,pD0,pD1) is begin
    if(rising_edge(CLK)) then
      pD0 <= D0; pD1 <= D1;
      if(pD0&D0="01") then
        SEQ <= SEQ(6 downto 0) & '0';
      elsif(pD1&D1="01") then
        SEQ <= SEQ(6 downto 0) & '1';
      end if;
    end if;
  end process;
  LED <= SEQ;
end Behavioral;