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-- 2021-Fall Quiz 2
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity quiz2 is
    Port ( CLK : in  STD_LOGIC;
           btnL : in  STD_LOGIC;
           btnR : in  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (7 downto 0));
end quiz2;

architecture Behavioral of quiz2 is
  signal SR,SL: STD_LOGIC_VECTOR(7 downto 0);
  signal tmrcntr : integer range 0 to 12500000;
begin
  process(CLK,tmrcntr,btnL,btnR,SR,SL) is begin
    if(rising_edge(CLK)) then
      if(tmrcntr=12500000) then
        tmrcntr <= 0;
        SR <= (btnR xor SR(0)) & SR(7 downto 1);
        SL <= SL(6 downto 0) & (btnL xor SL(7));
      else
        tmrcntr <= tmrcntr +1;
      end if;
    end if;
  end process;
  LED <= SR or SL;
end Behavioral;