Some Xilinx ISE and VHDL-Design problems (and solutions, if exist) will be listed here. 

1. ISE 14.7 Crashes on File Open (Win64 platforms)

BackupCopy <ISE>\ISE\lib\nt64\libPortability.dll to <ISE>\ISE\lib\nt64\libPortability.dll.orig

Copy <ISE>\ISE\lib\nt64\libPortabilityNOSH.dll to <ISE>\ISE\lib\nt64\libPortability.dll

This solves the same problem in Impact.

2. Impact detects no USB/Platform cable

Reinstall cable drivers;

1. Plug-in the USB cable. Open Device Manager, Uninstall Xilinx Cable Driver with remove from disk option checked.

2. Remove USB cable.

3. Execute <ISE>\ISE\bin\nt64\install_drivers.exe

4. Plug-in the USB cable and see if the cable is found.

3. Inferring a Block RAM with record type  

You want to infer BRAM of record type like;

type MyRec is record

  D: STD_LOGIC_VECTOR(7 downto 0);

  Z: STD_LOGIC_VECTOR(1 downto 0);

end record;

type MemType is array (0 to 127) of MyRec;

signal Mem: MemType;

It seems Xilinx ISE/Vivado cannot handle that. See https://support.xilinx.com/s/article/52331?language=en_US

So, you have to handle combining record members to a vector and backwards (create the record from memory output data) manually.

type MemType is array (0 to 127) of STD_LOGIC_VECTOR(9 downto 0);

...

(somewhere in the code)

Din <= Rec1.D & Rec1.Z;

Rec2.D <= Dout(9 downto 2); Rec2.Z <= Dout(1 downto 0);

Otherwise, synthesizer will not use a BRAMs in device but create one using slice elements (and will take too long to synthesize even if it fits in the FPGA)(I hear you say WTF?).

4. "I messed up Default Startup Design on Spartan 3E Starter Kit . What do I do?"