VHDL / FPGA Lab Experiments

The following are the current in-lab experiments. Experiments, their order and content may change during the semester. Students may be asked to complete two experiments within a lab session. Students are required to attend all experiment sessions, do their experiments with groups of two students according to the lab flyers, turn in their lab reports within a day in lab report format. Only one make-up experiment is allowed, at the end of the semester.

1. Starting an ISE project (no report is asked)

2. 3 to 8 Decoder (experiment, report)

3. Up Counter (experiment, report)

4. Up-Down Counter, ISim (experiment, report)

5. Key Debouncing (homeworkexperiment, report)

6. Two Instances of a Counter (experiment, report)

6+. Two Counter Instances with de-bouncer (experimentreport

6++. Two BCD Counters with de-bouncer (experimentreport

7. Knight Rider with Buttons (experiment, report)

8. Generic Rotary Encoder (experiment, report)

9. Key Sequence Reader (experiment, report)

10. Another State Machine (experiment, report)

11. Block Memories (experiment, report)

12. Block Memories Inference (experiment, report)

13. SPI Communication (experiment, report)

14. Timed Outputs (experiment, report, debouncer.vhd)

15. For Loop (experiment, report)

16. Simple State Machine (experimentreport)